PRM48DH480T250A03 Datasheet, PDF (18/23 Pages) Vicor Corporation – Building block for high efficiency DC-DC systems

The current limit and overcurrent protection set points are
linked, and scale together against the current sense shunt,
and the gain of the current sense amplifier. The output of
the current sense IC provides the IF voltage which has
V_{IF_IL} and V_{IF_OC} thresholds for the two functions
respectively. The set points are therefore defined by:
I _IL
=
V_{IF _ IL}
R_S ⋅ G_CS
and
I _OC
=
V_{IF _ OC}
R_S ⋅ G_CS
where G_CS is the gain of the current sense amplifier.
9.2.3 Control loop compensation requirements
In order to properly compensate the control loop, all
components which contribute to the closed loop frequency
response should be identified and understood. Figure 25
shows the AC small signal model for the module.
Modulator DC gain G_PR and powertrain equivalent
resistance r_{EQ_OUT} are shown. These modeling parameters
will support a design cut-off frequency up to 50 kHz.
Standard Bode analysis should be used for calculating the
error amplifier compensation and analyzing the closed
loop stability. The recommended stability criteria are as
follows:
1) Phase Margin > 45º : for the closed loop response, the
phase should be greater than 45º where the gain crosses
0dB.
2) Gain Margin > 10dB : The closed loop gain should be
lower than -10dB where the phase crosses 0º.
3) Gain Slope = -20dB / decade : The closed loop gain
should have a slope of -20dB / decade at the crossover
frequency.
The compensation characteristics must be selected to
meet these stability criteria. Refer to Figure 27 for a local
sense, voltage-mode control example based on the
configuration in Figure 26. In this example, it is assumed
that the maximum crossover frequency (F_CMAX) has been
selected to occur between B and C. Type-2 compensation
(Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
Ø Modulator Gain G_PR: See Figures 17, 18, 19
Ø Powertrain equivalent resistance r_EQ: See Figures
17, 18, 19
Ø Internal output capacitance: see Figure 20
Ø External output capacitance value
PRM48DH480T250A03
In the case of ceramic capacitors, the ESR can be
considered low enough to push the associated zero well
above the frequency of interest. Applications with high
ESR capacitor may require a different type of
compensation, or cascade control.
The system poles and zeros of the closed loop can then
be defined as follows:
Ø Powertrain pole, assuming the external capacitor
ESR can be neglected:
R << _{rr +}^{⋅ RR} _{COUT _ EXT}
EQ _ OUT
EQ _ OUT
LOAD
LOAD
Ø Main pole frequency:
( ) ^FP
≈
2 π⋅
r_{EQ _ OUT} ⋅ R_LOAD
r_{EQ _ OUT} + R_LOAD
1
⋅
C + C _{OUT _ INT}
OUT _ EXT
Ø Compensation Mid-Band Gain:
G _MB
=
20 log
R₃
R₁
[1]
Ø Compensation Zero:
1
F_Z1 = _{2 π⋅ R3⋅ C1}
[2]
Ø Compensation Pole:
1
F_P2 = _{2 π⋅ R3 ⋅ C1 ⋅ C2}
C₁ + C₂
and for F_P2>>F_Z1 (C₁ + C₂ ≈ C₁):
F_{P 2}
≈
2π
1
⋅ R₃
⋅ C₂
[3]
PRM^® Regulator  
 
Rev 1.4  
 
vicorpower.com  
Page 18 of 23    
 
12/2012    
 
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