CD-700-SYNCE-25M0000000 Datasheet, PDF (7/11 Pages) Vectron International, Inc – Complete VCXO Based Phase Lock Loop

***** VCXO, Input Bandwidth=50kHz
r5 7 8 160k
c4 8 0 20p
*****VCXO Gain x 2Π (Example: 19.440 MHz x 100 ppm x 2 x Π)
e4 9 0 8 0 12214
*****1/S model
r6 9 10 1000
c5 10 11 0.001u
e5 11 0 10 0 –1e6
****Divide by n
e6 12 0 11 0 1
r7 12 0 1k
The bold numbers are user selectable R and C values that will vary depending on the application (see Figure 11).
Layout Considerations
To achieve stable, low noise performance good analog layout techniques should be incorporated and a partial list is shown below.
The CD-700 should be treated more like an analog device and the power supply must be well decoupled with a good quality RF
0.01 uF capacitor in parallel with a 0.1 uF capacitor, located as close to pin 14 as possible and connected to ground. In some cases,
a PI filter such as a large capacitor (10uF) to ground, a series ferrite bead or inductor with 0.01 uF and 100 pF capacitor to ground
to decouple the device supply.
The traces for the OUT1, OUT2, RCLK and RDATA ouputs should be kept as short as possible. It is common practice to use a series
resistor ( 50 to 100 ohms ) in order to reduce reflections if these traces are more than a couple of inches long. Also OUT1, OUT2,
RCLK and RDATA should not be routed directly underneath the device.
The op-amp loop filter components should be kept as close to the device as possible and the feedback capacitor should be
located close to the op-amp input terminal. The loop filter capacitor(s) should be low leakage (polarized capacitors are allowed).
Unused outputs should be left floating and it is not required to load or terminate them (such as an ECL or PECL output). Loading
unused outputs will only increase current consumption.
Page 7 of 11
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 15Dec2009