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CD-700-SYNCE-25M0000000 Datasheet, PDF (10/11 Pages) Vectron International, Inc – Complete VCXO Based Phase Lock Loop
Table 7. Pin Functions
Pin
Symbol
1
OPOUT
2
OPN
3
PHO
4
LOSIN
5
DATAIN
6
CLKIN
7
GND
8
LOS
9
RCLK
10
RDATA
11
OUT2
12
HIZ
13
OUT1
14
V
DD
15
OPP
16
V
C
Figure 12. Outline Diagram
Op-Amp Output
Function
Op-Amp Negative Input
Phase detector Output
INPUT (Used with LOS)
Logic 0, VCXO control voltage is enabled.
Logic 1, VCXO control voltage (pin 16) is disabled and OUT1 and OUT2 are within +/-75 ppm of center
frequency
Has Internal pull-down resistor
Phase detector Input signal (TTL switching thresholds)
Phase detector Clock signal (TTL switching thresholds)
Cover and Electrical Ground
OUTPUT (Used with LOSIN)
Logic 1 if there are no transitions detected at DATAIN after 256 clock cycles at CLKIN. As soon as a transi-
tion occurs at DATAIN, LOS is set to a logic low.
Logic 0 = Input frequency detected
Recovered Clock
Recovered Data
Divided-down VCXO Output, or Disabled
INPUT
Logic 0, OUT1, OUT2, RCLK, RDATA are set to a high impedance state.
Logic 1, OUT1, OUT2, RCLK, RDATA are active.
Has Internal pull-up resistor
VCXO Output
Power Supply Voltage (3.3 V ±10% or 5.0 V ±10%)
Op-Amp Positive Input
VCXO Control Voltage
Page 10 of 11
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 15Dec2009