CD-700-SYNCE-25M0000000 Datasheet, PDF (2/11 Pages) Vectron International, Inc – Complete VCXO Based Phase Lock Loop

Performance Specifications
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical Maximum
Units
Output Frequency
OUT 1, 3.3 V option
OUT 2, 3.3V option
50.0
MHz
25.0
MHz
Supply Voltage¹
+3.3
V
DD
2.97
3.3
3.63
V
Supply Current
Output Logic Levels
Output Logic High²
Output Logic Low²
Output Transition Times
Rise Time²
Fall Time²
Input Logic Levels
Input Logic High²
Input Logic Low²
Loss of Signal Indication
Output Logic High²
Output Logic Low²
Nominal Frequency on Loss of Signal
Output 1
Output 2
I
DD
V
2.5
OH
V
OL
t
R
t_F
V
2.0
IH
V
IL
V_OH
2.5
V
OL
63
mA
V
0.5
V
3.0
ns
3.0
ns
V
0.5
V
V
0.5
V
±75
ppm
±75
ppm
Symmetry or Duty Cycle³
Out 1
Out 2
RCLK
SYM1
SYM2
RCLK
40/60
%
45/55
%
40/60
%
Absolute Pull Range
APR
±100
ppm
over operating temperure, aging, and power
supply variations
Jitter Generation - 25 MHz output
(12kHz - 20MHz BW)
Test Conditions for APR (+3.3 V option)
Gain Transfer
Φ
340
600
fsec-rms
J
V
0.3
C
3.0
V
Kv
Positive
Phase Detector Gain
+3.3 V
Kv
0.35
rad/V
Operating temperature
T
-40/85
°C
OP
Control Voltage Leakage Current
I
VCXO
±1.0
μA
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which these parameters
are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Page 2 of 11
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA Test Conditions (25 ±50C)
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 15Dec2009