UR5596_10 Datasheet, PDF (9/12 Pages) Unisonic Technologies – DDR TERMINATION REGULATOR

UR5596
CMOS IC
„ TYPICAL APPLICATION CIRCUITS(Cont.)
FOR DDR-II APPLICATIONS
As a result of the separate V_DDQ pin and an internal resistor divider, UR5596 can be utilized in DDR-II system,
figure 5 and 6 show two recommended circuits in DDR-II SDRAM application. The output stage is connected to the
1.8V rail and the AV_IN pin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is
possible to connect the output stage to a 3.3V rail. The power dissipation increasing concern must be careful as well
SSTL-II application. The advantage of configuration of figure 6 is that it has the ability to source and sink a higher
maximum continuous current.
Figure 5. Recommended DDR-II Termination
SHDN
VDDQ=1.8V
AVIN=3.3V or 5.5V
PVIN=3.3V
+
CIN
UTC UR5596
SHDN
V_DDQ
AVIN
V_REF
V_SENSE
PVIN
V_TT
GND
+
CREF
VREF=0.9V
+
COUT
VTT=0.9V


Figure 6. DDR-II Termination with higher voltage rails
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
9 of 12
QW-R502-045,C