UR5596_10 Datasheet, PDF (6/12 Pages) Unisonic Technologies – DDR TERMINATION REGULATOR

UR5596
CMOS IC
„ CAPACITOR SELECTION
A capacitor is recommended for improve performance during large load transients to prevent the input rail from
dropping, even though UR5596 does not require for input stability. The input capacitor should be located as close as
possible to the PV_IN pin. The typical recommended value for AL electrolytic capacitors is 50 µF and 10 µF with X5R
or better for Ceramic capacitors. If AV_IN and PV_IN are separated, the 47µF capacitor should be placed as close to
possible to the PV_IN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive
noise from coupling into the device.
UTC UR5596 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).
The choice for output capacitor depends on the application and the requirements for load transient response of V_TT.
As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL
applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected
and the extent at which the output voltage is allowed to droop.
„ THERMAL DISSIPATION
The UR5596 will generate heat result from internal power dissipation when current flow working. The device might
be damaged any beyond maximum junction temperature rating. The maximum allowable internal temperature rise
(T_Rmax) can be calculated given the maximum ambient temperature (T_Amax) of the application and the maximum
allowable junction temperature (T_Jmax).
T_Rmax = T_Jmax − T_Amax
From this equation, the maximum power dissipation (P_Dmax) of the part can be calculated:
P_Dmax = T_Rmax / θ_JA
The θ_JA of UR5596 can be calculated (refer to JEDEC standard) and will depend on several package type,
materials, ambient air temperature and so on.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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