UR5596_10 Datasheet, PDF (7/12 Pages) Unisonic Technologies – DDR TERMINATION REGULATOR

UR5596
CMOS IC
„ TYPICAL APPLICATION CIRCUITS
Following demonstrate several different application circuits to illustrate some of the options that are possible in
configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance
Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AV_IN and PV_IN.
STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME
SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination
scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered
with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one
R_S series resistor from the chipset to the memory and one R_T termination resistor (refer to Figure 1). R_S and R_T are
changeable to meet the current requirement from UR5596, the recommended values both R_S and R_T are 25Ƹ
Figure 1. SSTL-Termination Scheme
FOR SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all
the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and
component count and selection.
UTC UR5596
SHDN
VDDQ=2.5V
VDD=2.5V
SHDN
V_DDQ
AVIN
V_REF
V_SENSE
+
CREF
VREF=1.25V
CIN
+
PVIN
V_TT
GND
+
COUT
VTT=1.25V
Figure 2. Recommended SSTL-2 Implementation
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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