UR5596_10 Datasheet, PDF (8/12 Pages) Unisonic Technologies – DDR TERMINATION REGULATOR

UR5596
CMOS IC
„ TYPICAL APPLICATION CIRCUITS(Cont.)
Figure 3 illustrate another application that the power rails are split when power dissipation or efficiency are
concerned. The output stage (PV_IN) can be as lower as 1.8V, and the analog circuitry (AV_IN) can be connected to a
higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current
from V_TT, but the disadvantage of this circuit is the maximum continuous current is reduced.
SHDN
VDDQ=2.5V
AVIN=2.2V ~ 5.5V
PVIN=1.8V
CIN
+
UTC UR5596
SHDN
V_DDQ
AVIN
V_REF
V_SENSE
PVIN
V_TT
GND
+
CREF
VREF=1.25V
+
COUT
VTT=1.25V
Figure 3. Lower Power Dissipation SSTL-2 Implementation
The third optional application is that PV_IN connect to 3.3V and AV_IN will be always limited to operation on the 3.3V
or 5V to always equal or higher than PV_IN. This configuration has the ability to provide the maximum continuous
output current at the downside of higher thermal dissipation. The power dissipation increasing problem must be
careful to prevent the junction temperature to exceed the maximum ranting. Because of this risk it is not
recommended to supply the output stage with a voltage higher than a nominal 3.3V rail.
UTC UR5596
SHDN
VDDQ=2.5V
AVIN=3.3V or 5.5V
SHDN
V_DDQ
AVIN
V_REF
V_SENSE
+
CREF
VREF=1.25V
PVIN=3.3V
CIN
+
PVIN
V_TT
GND
+
COUT
VTT=1.25V
Figure 4. SSTL-2 Implementation with higher voltage rails
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
8 of 12
QW-R502-045,C