TCD6000 Datasheet, PDF (18/36 Pages) Tripath Technology Inc. – 6 CHANNEL CLASS-T DIGITAL AUDIO PROCESSOR USING DIGITAL POWER PROCESSINGTM TECHNOLOGY

Tripath Technology, Inc. – Preliminary Technical Information
During a Sync Reset the DATAnn inputs are ignored and digital silence is substituted. The TCD6000 waits
for the clocks to be synchronized before coming out of reset. During Sync Reset, the internal automatic DC
offset calibration values are cleared. When the clocks are restored, the system will need to be re-calibrated
by hard muting and un-muting or by forcing a DC calibration value in the Calibration Bank.
The Sync Reset is different from an external reset, which is created by pulling the RESETB pin low. A Sync
Reset will not change the values of I2C addressable read/write registers.
R1 enables a “Hard-mute” upon Sync Reset. When the Sync Reset condition is removed, an auto-calibration
will take place before the outputs are restored. R0 must be set to ‘1’ for R1 to have any effect.
The Master Clock (MCK) input frequency is determined by a combination of the S4X, S2X, and HFR bits and
the sampling frequency. The phase of MCK is not critical, as long as the frequency is correctly set. When the
HFR bit (register 23h, bit D3) is set to ‘1’, the TCD6000 divides MCK by 2 so that higher frequency system
clocks may be used. The duty cycle of MCK should be between 48% and 52% unless HFR is set to ‘1’. In
this case, the division automatically creates a 50% duty cycle internal clock.
HFR
0
0
0
0
1
1
1
1
S4X
S2X
MCK pulses
per sample
0
0
256
0
1
128
1
0
64
1
1
64
0
0
512
0
1
256
1
0
128
1
1
128
The following table shows some examples of the MCK clock frequency based on sampling rate and HFR:
Data sampling rate
MCK frequency (HFR = ‘0’)
MCK frequency (HFR = ‘1’)
32 kHz
8.192 MHz
16.384 MHz
44.1 kHz
11.289 MHz
22.578 MHz
48 kHz
12.288 MHz
24.576 MHz
96 kHz
12.288 MHz
24.576 MHz
192 kHz
12.288 MHz
24.576 MHz
Digital Input Format
Addr
24h
Register Name
Digital Input Format
Default
D7 D6
D5
D4
D3
D2
D1
D0
0
DP BCK CCK I2S LRA DW1 DW0
0
0
1
0
0
0
1
1
This register allows the user to specify the following digital interface characteristics:
- Input data width (DW0 and DW1)
- Input data alignment with respect to LRCK clock edges (LRA)
- Polarity of the LRCK clock (CCK)
- Polarity of the BITCK clock (BCK)
- Polarity of the input data (DP)
The TCD6000 receives PCM digital audio data in I2S format or variations thereof. The format consists of an
audio data input (DATAnn), a bit clock (BITCK) that runs at 64x the sampling frequency, and a 1x sampling
frequency clock (LRCK). In addition, a master clock (MCK) synchronizes all digital operations inside the
device. Each DATAnn input carries serial data for 2 channels. The LRCK clock differentiates between odd
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TCD6000 – Rev. 1.0/09.04