TCD6000 Datasheet, PDF (10/36 Pages) Tripath Technology Inc. – 6 CHANNEL CLASS-T DIGITAL AUDIO PROCESSOR USING DIGITAL POWER PROCESSINGTM TECHNOLOGY

PREDICTIVE GAIN CONTROL
Tripath Technology, Inc. – Preliminary Technical Information
The Predictive Gain Control (PGC) automatically sets one of four different pre-gain levels depending on the
Channel Volume level (registers 25h – 2Ah). The PGC allows less gain to be used for lower volume levels.
This results in greater digital resolution and lower noise floor. When PGC is enabled (register 3Dh bit D7 is
set to ‘1’), PGC settings are changed automatically by the Channel Volume. When PGC is disabled, the
system’s pre-gain level is always set to full gain.
Channel Volume Range
FFh – F4h
F3h – E8h
E7h – DCh
DBh – 00h
PGC Setting
Full Gain
1/2 Gain
1/4 Gain
1/8 Gain
POST-GAIN
When the GNn control bits are cleared to ‘0’, the TCD6000 operates in low post-gain mode. In this mode,
the noise floor is lowered but the system may not be able to obtain the maximum power output from the
power stage. When the GNn control bits are set to ‘1’, the TCD6000 operates in high post-gain mode. In this
mode, gain is increased by 25% (about 2dB). The system will now be able to obtain the maximum power
output from the power stage but the noise floor will have increased accordingly.
The user may use low post-gain at low volume levels to take advantage of the lower noise floor and use high
post-gain at higher volume levels to take advantage of the full range of the power stage. Precautions must
be taken while changing post-gain to prevent DC offset. The automatic DC offset cancellation settings will
have been affected by changes in post-gain. To avoid this problem, the software that is controlling the
TCD6000 through the I²C port should store DC calibration values for each post-gain setting and swap
between them as in the following procedure:
1. Set post-gain to low and channel volumes to 00h.
2. Un-mute.
3. Wait for calibration to complete.
4. Read values in the “Calibration Readback” registers and write them to the “Calibration Bank”
registers.
5. Mute.
6. Set post-gain to high and channel volumes to 00h.
7. Un-mute.
Now the calibration bank contains the DC calibration values for low post-gain and the TCD6000 has stored
the DC calibration values for high post-gain in its internal registers. When the CFn bits (register 2Fh bits
D5..D0) are set to ‘1’, the values stored in the Calibration Bank are used. When the CFn bits are cleared to
‘0’, the internal registers that hold the automatic DC calibration values for high post-gain are used. If the
PGC is enabled, the software should only switch between low and high post-gain modes when the PGC is in
1/8 Gain mode. This is because the values stored in the Calibration Bank will only be valid for the PGC
mode that was in effect when the channel volumes were set to 00h and automatic DC calibration took place.
Special care should be taken when using this scheme to prevent events from interfering with DC calibration.
FAULT should be latched so that a proper calibration can take place during un-mute. Clocks should be kept
synchronized to prevent Sync Reset.
I²C INTERFACE
The I²C interface is a simple bi-directional bus interface for allowing a microcontroller to read and write
control registers in the TCD6000. Every component hooked up to the I²C bus has its own unique address
whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver
and/or transmitter depending on its functionality. The TCD6000 acts as a slave while a microcontroller would
act as a master.
The TCD6000 device address is 80h, 82h, 84h, or 86h depending on the state of the ADDRn pins. The
TCD6000 constantly monitors the I²C data input and waits until its device address appears before writing
into or reading from its control registers. The 8^th bit of the address determines whether the master is reading
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TCD6000 – Rev. 1.0/09.04