TCD6000 Datasheet, PDF (17/36 Pages) Tripath Technology Inc. – 6 CHANNEL CLASS-T DIGITAL AUDIO PROCESSOR USING DIGITAL POWER PROCESSINGTM TECHNOLOGY

Tripath Technology, Inc. – Preliminary Technical Information
0.5
0.4
0.3
0.2
0.1
0
-0 .1
-0 .2
-0 .3
-0 .4
-0 .5
0
Total Effective D roop, After C orrection
1x mode
2x mode
4x mode
2
4
6
Frequency in kHz
8
10
4
x 10
Figure 3. Frequency response of the Droop Correction Filter
Sampling Rate Control
Addr
22h
Register Name
Sampling Rate Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1Xf 1Xs
0
S4X S2X
0
0
0
0
0
0
0
0
This register allows the user to specify the data-sampling rate (1X, 2X or 4X). When the 1X mode is selected
and the de-emphasis filter is enabled, 1Xf and 1Xs select between 32 kHz, 44.1kHz, and 48 kHz de-
emphasis filters.
Bits S4X S2X
0
0
0
1
1 0 or 1
1X mode (32 kHz, 44.1 kHz, or 48 kHz)
2X mode (96 kHz)
4X mode (192 kHz)
Bits 1Xf 1Xs
0
0
0
1
1
0
1
1
data-sampling rate is 44.1 kHz
data-sampling rate is 32 kHz
data-sampling rate is 48 kHz
not used
If the 2X or the 4X modes are selected, the de-emphasis filter is automatically disabled, and the setting of bit
D6 in the Filter Bypass Control register (address 21h) will be ignored.
Operation Control
Addr
23h
Register Name
Operation Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
HFR
0
R1
R0
0
1
0
0
0
0
1
1
This register allows the user to specify 2 operational characteristics of the TCD6000:
- The Sync Reset mode (control bits R0 and R1)
- The High Frequency Master Clock option (control bit HFR)
If the Left/Right channel clock (LRCK) and Bit clock (BITCK) are not properly synchronized with the Master
clock (MCK) and R0 is set to ‘1’, a “Sync Reset” is generated. If R1 is also set to ‘1’ a hard mute is issued
during the Sync Reset and released after the Sync Reset is released.
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TCD6000 – Rev. 1.0/09.04