TA1360AFG Datasheet, PDF (91/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

TA1360AFG
Note
No.
Characteristics
SW68
T33 OSD ACL
A
characteristic
SW67
B
SW66
B
Test Conditions
SW Mode
SW26 SW25 SW24
A
A
A
SW21
A
SW19
A
SW18
B 1.
Test Method
Input signal 1(f₀ = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive
gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12.
2. Set subaddress (07) data to (01).
3. Apply 5-V external voltage to pins 1 and 80.
4. Input signal 1 (f₀ = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18.
5. Measure pin 12 picture period amplitude, vOSDACL1.
6. Apply “pin 78 DC voltage − 0.8 V” to pin 78 from external power supply, and measure pin
12-picture period amplitude, vOSDACL2.
7. Apply “pin 78 DC voltage − 1.3 V” to pin 78 from external power supply, and measure pin
12-picture period amplitude, vOSDACL3.
8. OSDACL₁ = −20 × log (vOSDACL2/vOSDACL1)
OSDACL₂ = −20 × log (vOSDACL3/vOSDACL1)
9. OSDACL3ɺOSDACL4 Change subaddress (07) data to (80), and repeat the steps 6 to 8
above to measure OSDACL3 and OSDACL4.
91
2003-01-21