TA1360AFG Datasheet, PDF (23/110 Pages) Toshiba Semiconductor – YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV

Data Transmit Format 1
TA1360AFG
S Slave address 0 A
7 bit
Sub address
8 bit
MSB
S: Start condition
MSB
A: Acknowledgement
A Transmit data A P
9 bit
MSB
P: Stop condition
Data Transmit Format 2
S Slave address 0 A Sub address A Transmit data 1 A ŋŋŋŋŋŋç
ŋŋŋŋŋŋ
Sub address A Transmit data n A P
Data Receive Format
S Slave address
7 bit
MSB
1 A Transmit data 1 A
8 bit
MSB
Receive data 2
AP
To receive data, the master transmitter changes to the receiver immediately after the first acknowledgement.
The slave receiver changes to the transmitter.
The stop condition is always created by the master.
Details are provided in the Philips I²C specifications.
Optional Data Transmit Format
S Slave address
7 bit
MSB
0A1
Sub address
7 bit
MSB
A Transmit data 1
8 bit
MSB
ŋŋŋŋ Transmit data n
8 bit
MSB
AP
In this way, sub addresses are automatically incremented from the specified sub address and data are set.
Purchase of TOSHIBA I²C components conveys a license under the Philips I²C Patent Rights to use these
components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by
Philips.
23
2003-01-21