TC9WMA2FK Datasheet, PDF (9/15 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic 2,048-Bit (256 × 8 Bit) Serial E2PROM

TC9WMA2FK
A.C. Characteristics (V_CC = 1.8 to 2.7 V, GND = 0 V, T_opr = −40 to 85°C)
Characteristics
Maximum clock frequency
Minimum clock pulse width
Minimum reset pulse width
Minimum chip select pulse
width
Reset setup time
Clock setup time
CS setup time
Propagation delay time
(Note)
Input data setup time
Input data hold time
Symbol
Test Condition
f_MAX
twCLK (L)
twCLK (H)
t_WRST
t_WCS
t_RSS
t_CKS
t_CSS
t_pLH
t_pHL
t_pZH
t_pZL
t_pLZ
t_pHZ
t_s
t_h
RST setup time when
CS is switched over
CLK setup time
when CS is switched
over
CS setup time when
CLK is switched over
Time from CLK
switchover until valid
data is output
Time from CS
switchover until output
data goes Hi-Z
Input data setup time
when CLK is
switched over
Input data hold time
when CLK is
switched over
1.8 V ^<= V_CC < 2.3 V
Min
Max
0
0.25
1.0
⎯
1
⎯
1
⎯
1
⎯
500
⎯
500
⎯
⎯
2.0
⎯
2.0
500
⎯
500
⎯
2.3 V ^<= V_CC < 2.7 V
Min
Max
0
0.5
1.0
⎯
1
⎯
1
⎯
1
⎯
500
⎯
500
⎯
⎯
1.0
⎯
1.0
500
⎯
500
⎯
Note: C_L = 100 pF, R_L = 1 kΩ
Unit
MHz
μs
μs
μs
μs
ns
ns
μs
ns
ns
9
2007-10-19