JBT6L77-AS Datasheet, PDF (9/20 Pages) Toshiba Semiconductor – Source Driver for TFT LCD Panels

JBT6L77-AS
Device Operation
(1) Starting data transfer
A high input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic synchronously
with the rising edge of CPH, setting the device ready to transfer data. Data transfer starts at the next rise of
CPH (see Timing diagram 1 and 2).
(2) Data transfer method
The data is latched in from the grayscale bus to the sampling register synchronously with each rising edge of
CPH.
Grayscale data for three outputs are latched into the device simultaneously in one transfer.
Grayscale data are written as three outputs in parallel during one transfer. Data transfer completes after 80
transfers. Then the device enters Standby mode.
Data written to the sampling register are the operation result of the grayscale data bus.
(3) Terminating data transfer
The data transfer enable pin (DO/I or DI/O) output goes high synchronously with the rising edge of CPH one
clock period before the last data is latched in. It is held high until the next rise of CPH (see Timing diagram
1 and 2).
The output from this pin can be connected directly as input to the data transfer enable pin (DI/O or DO/I) of
the next stage LCD driver. In this way, multiple devices can be easily cascaded to drive a large screen.
(4) Panel drive output
When a high voltage supplies to the load input, the data in the sampling register is transferred to the load
register and the device starts updating output to the LCD panel drive pins.
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2001-12-18