JBT6L77-AS Datasheet, PDF (8/20 Pages) Toshiba Semiconductor – Source Driver for TFT LCD Panels

Pin Function
Pin Name
DI/O
DO/I
U/D
CPH
DA0 to DA5
DB0 to DB5
DC0 to DC5
LOAD
V0 to V10
TESTB
SA1 to SA80
SB1 to SB80
SC1 to SC80
AV_DD
DV_DD
V_SS
JBT6L77-AS
I/O
Function
Data transfer enable pin
These pins are used to input/output grayscale data.
Input and output are switched as shown below according to the setting of the U/D pin.
U/D
DI/O
DO/I
H
Input
Output
I/O
L
Output
Input
When set for input
A high on DI/O or DO/I is latched into the internal logic synchronously with the rising edge of
CPH. When the internal circuit is in standby state, the device is ready to transfer data.
The grayscale data is latched in sequentially, starting at the next rise of CPH.
When set for output
The pin is used to transfer the enable signal to the JBT6L77-AS at the next stage of the LCD
driver.
The pin enters standby state after outputting a high.
Transfer direction select pin
This pin controls the direction in which the data is transferred into the sampling register.
Data is transferred synchronously with each rising edge of CPH in one of the following
sequences:
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When U/D is high, data is transferred in the order SA1 to SC1, SA2 to SC2, SA3 to SC3, …
When U/D is low, the direction is reversed to give SA80 to SC80, SA79 to SC79,
SA78 to SC78, …
The voltage applied to this pin must be a DC-level voltage that is either high or low.
Sampling clock input
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This clock input is used to transfer grayscale data.
In sync with the rising edge of CPH, writes grayscale data bus data to the sampling register.
Grayscale data bus
The data inputs consist of 6-bit word for each three channel that are transferred in parallel at the
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rising edge of CPH. The relationship between the grayscale data and the weight of each bit is
as follows:
Grayscale data = 32 ´ Dw5 + 16 ´ Dw4 + 8 ´ Dw3 + 4 ´ Dw2 + 2 ´ Dw1 + Dw0
(*) w = A, B, C
Data load input pin
When a high voltage supplys to the load input, the data is transferred from the Sampling register
to the Load register synchronously at the rising edge of CPH.
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(Note) After High level is input to this pin (LOAD), input CPH for at least three cycles in the
same cycle as that for sampling.
· When LOAD = Low level, output is at high impedance.
· When LOAD = High level, output corresponds to grayscale data.
Reference analog input pins
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These pins are used to input the voltage used for the DAC.
V_SS < V0 ^<= V1 ^<= … ^<= V9 ^<= V10 < AVDD or AVDD > V0 ^>= V1 ^>= … ^>= V9 ^>= V10 > V_SS
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Test pin
Leave this pin open or V_DD level.
O
LCD panel drive pins
Analog power supply pin
Digital power supply pin.
GND pin
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2001-12-18