TMP19A43CD Datasheet, PDF (81/523 Pages) Toshiba Semiconductor – 32-bit RISC Microprocessor

TMP19A43
6.9 INTCG Registers (Interrupts to Clear STOP, SLEEP, and IDLE)
IMCGA
(0xFFFF_EE10)
INT0 to INTB, KWUP0 to 31 (Interrupts to Clear Stop, Sleep, and Idle modes)
INTRTC, INTTB2, 3 (Two-phase pulse input counter): Sleep
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
7
R
0
Always
reads "0."
15
R
0
Always
reads "0."
23
R
0
Always
reads "0."
31
R
0
Always
reads "0."
6
5
4
EMCG02 EMCG01 EMCG00
R/W
0
1
0
Set active state of INT0 standby
clear request.
000: "L" level
001: "H" level
010: Falling edge
011: Rising edge
100: Both edges
14
13
12
EMCG12 EMCG11 EMCG10
R/W
0
1
0
Set active state of INT1 standby
clear request.
000: "L" level
001: "H" level
010: Falling edge
011: Rising edge
100: Both edges
22
21
20
EMCG22 EMCG21 EMCG20
R/W
0
1
0
Set active state of INT2 standby
clear request.
000: "L" level
001: "H" level
010: Falling edge
011: Rising edge
100: Both edges
30
29
28
EMCG32 EMCG31 EMCG30
R/W
0
1
0
Set active state of INT3 standby
clear request.
000: "L" level
001: "H" level
010: Falling edge
011: Rising edge
100: Both edges
3
2
EMST01 EMST00
R
0
0
Active status of INT0
standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
11
10
EMST11 EMST10
R
0
0
Active status of INT1
standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
19
18
EMST21 EMST20
R
0
0
Active status of INT2
standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
27
26
EMST31 EMST30
R
0
0
Active status of INT3
standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
1
R
0
Always
reads "0."
9
R
0
Always
reads "0."
17
R
0
Always
reads "0."
25
R
0
Always
reads "0."
0
INT0EN
R/W
0
INT0
Clear
input
0: Disable
1: Enable
8
INT1EN
R/W
0
INT1
Clear
input
0: Disable
1: Enable
16
INT2EN
R/W
0
INT2
Clear
input
0: Disable
1: Enable
24
INT3EN
R/W
0
INT3
Clear
input
0: Disable
1: Enable
TMP19A43 (rev2.0) 6-46
Exceptions/Interrupts