TMP19A43CD Datasheet, PDF (216/523 Pages) Toshiba Semiconductor – 32-bit RISC Microprocessor

TMP19A43
10.4 Functions
The DMAC is a 32-bit DMA controller capable of transferring data in a system using the TX19A processor core
at high speeds without routing data via the core.
10.4.1 Overview
(1) Source and destination
The DMAC handles data transfers from memory to memory and between memory and an I/O
device. A device from which data is transferred is called a source device and a device to which data
is transferred is called a destination device. Both memory and I/O devices can be designated as a
source or destination device. The DMAC supports data transfers from memory to I/O devices, from
I/O devices to memory, and from memory to memory, but not between I/O devices.
The differences between memory and I/O devices are in the way they are accessed. When
accessing an I/O device, the DMAC asserts a DACKn signal. Because there is only one line per
channel that carries a DACKn signal, the number of I/O devices accessible during data transfer is
limited to one. Therefore, data cannot be transferred between I/O devices.
An interrupt factor can be attached to a transfer request to be sent to the DMAC. If an interrupt
factor is generated, the interrupt controller (INTC) issues a request to the DMAC (the TX19A
processor core is not notified of the interrupt request. For details, see description on Interrupts.).
The request issued by the INTC is cleared by the DACKn signal. Therefore, a request made to the
DMAC is cleared after completion of each data transfer (transfer of the amount of data specified by
TrSiz) if a single transfer is designated to select a transfer type (SIO BIT). On the other hand,
during a continuous transfer, the DACKn signal is asserted only when the number of bytes
transferred (value set in the BCRn register) becomes "0." Therefore, one transfer request allows
data to be transferred successively without a pause.
For example, if data is transferred between a internal I/O and the internal (external) memory of the
TMP19A43, a request made by the internal I/O to the DMAC is cleared after completion of each
data transfer and the transfer operation is always put in a standby mode for the next transfer request
if the number of bytes transferred (value set in the BCRn register) does not become "0." Therefore,
the DMA transfer operation continues until the value of the BCRn register becomes "0."
(2) Bus control arbitration (bus arbitration)
In response to a transfer request made inside the DMAC, the DMAC requests the TX19A processor
core to arbitrate bus control authority. When a response signal is returned from the core, the
DMAC acquires bus control authority and executes a data transfer bus cycle.
In acquiring bus control for the DMAC, use or nonuse of the data bus of the TX19A processor core
can be specified; specifically either snoop mode or non-snoop mode can be specified for each
channel by using bit 11 (SReq) of the CCRn register.
There are cases in which the TX19A processor core requests the release of bus control authority.
Whether or not to respond to this request can be specified for each channel by using the bit 10
(RelEn) of the CCRn register. However, this function can only be used in non-snoop mode
(GREQ). In snoop mode (SREQ), the TX19A processor core cannot request the release of bus
control and, therefore, this function cannot be used.
When there are no more transfer requests, the DMAC releases control of the bus. When there are
no more transfer requests, the DMAC releases the bus control.
(Note 1) Do not bring the TX19A to a halt when the DMAC is in operation.
(Note 2) To put the TX19A into IDLE (doze) mode when the snoop function is being used, you must
first stop the DMAC.
TMP19A43 (rev2.0) 10-20
DMA Controller (DMAC)