TMP19A43CD Datasheet, PDF (181/523 Pages) Toshiba Semiconductor – 32-bit RISC Microprocessor

TMP19A43
Fig. 8-13 shows the read operation timing when 0 wait, waits automatically inserted, and waits
automatically inserted + external waits are inserted in the multiplexed bus mode.
tsys
fsys
0 wait
A[23:16]
AD[15:0]
ALE
/RD
Higher-order address
Lower-order address
Data
/WAIT
2 waits automatically inserted
A[23:16]
AD[15:0]
ALE
/RD
Higher-order address
Lower-order address
Data
/WAIT
2 waits automatically inserted + 2N (N=1)
2 waits automatically
inserted
A[23:16]
Higher-order address
AD[15:0]
Lower-order address
Data
ALE
/RD
/WAIT
3 waits automatically inserted + 2N (N=1)
2 waits automatically 2N_WAIT
inserted
A[23:16]
Higher-order address
AD[15:0]
Lower-order address
Data
ALE
/RD
/WAIT
2 waits automatically inserted + 2N (N=2)
3 waits automatically
inserted
2N_WAIT
A[23:16]
Higher-order address
AD[15:0]
Lower-order address
Data
ALE
/RD
/WAIT
2 waits automatically
inserted
2N_WAIT
z --- External wait sampling point
External wait sampling points take place before a cycle of waits automatically
inserted is finished and before a 2N_wait cycle is finished as shown above.
The same applies to combinations of other numbers of waits.
Fig. 8-13 Read Operation Timing Diagram
TMP19A43 (rev2.0) 8-19
External Bus Interface