TMP89FW24AFG Datasheet, PDF (80/548 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C1 Series

3. Interrupt Control Circuit
3.4 Maskable Interrupt Priority Change Function
TMP89FW24A
3.4 Maskable Interrupt Priority Change Function
The priority of maskable interrupts (IL4 to IL30) can be changed to four levels, Levels 0 to 3, regardless of the
basic priorities 5 to 31. Interrupt priorities can be changed by the interrupt priority change control register
(ILPRS1 to ILPRS7). To raise the interrupt priority, set the Level to a larger number. To lower the interrupt prior-
ity, set the Level to a smaller number. When different maskable interrupts are generated simultaneously at the
same level, the interrupt with higher basic priority is processed preferentially. For example, when the ILPRS1 reg-
ister is set to 0xC0 and interrupts IL4 and IL7 are generated at the same time, IL7 is preferentially processed (pro-
vided that EF4 and EF7 have been enabled).
After reset is released, all maskable interrupts are set to priority level 0 (the lowest priority).
Note:In the main program, before manipulating the interrupt priority change control register (ILPRS1 to 7), be sure
to clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction).
Set the IMF to "1" as required after operating ILPRS1 to 7 (Enable interrupt by EI instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally.
However, if using multiple interrupt in the interrupt service routine, manipulate ILPRS1 to 7 before setting
the IMF to "1".
Interrupt priority change control register 1
ILPRS1
(0x00FF0)
Bit Symbol
Read/Write
After reset
7
6
IL07P
R/W
0
0
5
4
IL06P
R/W
0
0
3
2
IL05P
R/W
0
0
1
0
IL04P
R/W
0
0
IL07P
IL06P
IL05P
IL04P
Sets the interrupt priority of IL7.
Sets the interrupt priority of IL6.
Sets the interrupt priority of IL5.
Sets the interrupt priority of IL4.
00: Level 0 (lower priority)
01: Level 1
10: Level 2
11: Level 3 (higher priority)
Interrupt priority change control register 2
ILPRS2
(0x00FF1)
Bit Symbol
Read/Write
After reset
7
6
IL11P
R/W
0
0
5
4
IL10P
R/W
0
0
3
2
IL09P
R/W
0
0
IL11P
IL10P
IL09P
IL08P
Sets the interrupt priority of IL11.
Sets the interrupt priority of IL10.
Sets the interrupt priority of IL9.
Sets the interrupt priority of IL8.
00: Level 0 (lower priority)
01: Level 1
10: Level 2
11: Level 3 (higher priority)
1
0
IL08P
R/W
0
0
Interrupt priority change control register 3
ILPRS3
(0x00FF2)
Bit Symbol
Read/Write
After reset
7
6
IL15P
R/W
0
0
5
4
IL14P
R/W
0
0
3
2
IL13P
R/W
0
0
IL15P
IL14P
IL13P
IL12P
Sets the interrupt priority of IL15.
Sets the interrupt priority of IL14.
Sets the interrupt priority of IL13.
Sets the interrupt priority of IL12.
00: Level 0 (lower priority)
01: Level 1
10: Level 2
11: Level 3 (higher priority)
1
0
IL12P
R/W
0
0
2012/5/18
#!Undefined!#
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