TMP89FW24AFG Datasheet, PDF (427/548 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C1 Series

TMP89FW24A
24.3 Command Sequence
In MCU mode and serial PROM mode, the command sequence consists of seven commands, as shown in Ta-
ble 24-1.
Table 24-1 Command sequence
Command
sequence
1st Bus Write Cy- 2nd Bus Write Cy- 3rd Bus Write Cy- 4th Bus Write Cy- 5th Bus Write Cy- 6th Bus Write Cy-
cle
cle
cle
cle
cle
cle
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
PA
Data0
PA
Data1
PA
Data2
1
Page Program
0x#555
0xAA 0x#AAA
0x55
0x#555
0xA0
(Note 1)
(Note
2)
(Note1)
(Note
2)
(Note 1)
(Note
2)
Sector Eraase
2 _{(Partial Erase in Sec-} 0x#555
tor units )
0xAA 0x#AAA
0x55
0x#555
0x80
0x#555
0xAA
0x#AAA
0x55
SA
(Note 3)
0x30
Chip Erase
3
(All Erase)
0x#555 0xAA 0x#AAA 0x55 0x#555 0x80 0x#555 0xAA 0x#AAA 0x55 0x#555 0x10
4
Product ID Entry
0x#555 0xAA 0x#AAA 0x55 0x#555 0x90
-
-
-
-
-
-
5
Product ID Exit
0x#XXX 0xF0
-
-
-
-
-
-
-
-
-
-
6
Security Program
0x#555 0xAA 0x#AAA 0x55 0x#555 0x9A 0x#555 0xAA 0x#AAA 0x55 0x#555 0x9A
7
Security Erase
0x#555 0xAA 0x#AAA 0x55 0x#555 0x6A 0x#555 0xAA 0x#AAA 0x55 0x#555 0x6A
Command
7th Bus Write Cy- 8th Bus Write Cy- 9th Bus Write Cy-
cle
cle
cle
---
Sequence
Add
Data
Add
Data
Add
Data
---
130th Bus Write
Cycle
Add
Data
131th Bus Write
Cycle
Add
Data
PA
Data3
PA
Data4
PA
Data5
1
Page Program
(Note 1)
(Note
2)
(Note 1)
(Note
2)
(Note 1)
(Note
2)
Data
Data
---
PA
126
PA
127
(Note 1) _(Note (Note 1) _(Note
2)
2)
SB
6
Security Program
0x9A
-
-
-
-
---
(Note4)
-
-
-
-
7
Security Erase
0x#XXX 0x6A
-
-
-
-
---
-
-
-
-
Note 1: PA : Page address
Specify the beginning address of the PA to be written. Refer to Table 24-3 about the addressable address. As the
Page to be written is specified with the 4th address, addresses from 5th through 131st are not changed even if other
Page is specified.
Note 2: Set the data in size of 128bytes (1 Page).
Note 3: SA : Sector address
Specify the Sector address to be erased. Refer to Table 24-5 for further details about the addressable address.
Note 4: SB : Security address
Specify the address of the Security bits. Refer to Table 24-6 for further details about the addressable address.
Note 5: Do not start the STOP, IDLE0/1/2 or SLEEP1/0 mode while a command sequence is being executed or a task speci-
fied in a command sequence is being executed (write, erase or ID Entry).
Note 6: # ; 0x1 through 0xF must be specified with the upper 4bits of the address. However, while FLSCRM<BAREAM> is
set to "1", 0x2 or more must be specified. Usually, 0xF is recommended to be specified.
Note 7: Command sequences must be executed at 4 or more instruction cycles. If you use an instruction less than 4 instruc-
tion cycles, insert NOP instruction right after the write instruction to provide a instruction interval of 4 or more instruc-
tion cycle. A part of transfer instructions is shown in Table 24-2.
Note 8: The command sequence must be executed when the power supply source is turned ON (when
SDWCR1<FLSOFF>="0" and SDWCR1<FLSWUE>="1"). Even if the command sequence is executed when the pow-
er supply of the flash memory is OFF, the command is not accepted.
Note 9: X ; Don’t care
RA000
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2012/5/18