TMP89FW24AFG Datasheet, PDF (51/548 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C1 Series

TMP89FW24A
In the SLEEP0 mode, the peripheral circuits stop in the states when the SLEEP0 mode is activa-
ted or become the same as the states when a reset is released. For operations of the peripheral cir-
cuits in the SLEEP0 mode, refer to the section of each peripheral circuit.
The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode. The op-
eration returns to the SLOW1 mode after this mode is released.
In the SLEEP0 mode, the CPU stops and the timing generator stops the clock supply to the periph-
eral circuits except the time base timer.
2.3.5.3 STOP mode
In this mode, all the operations in the system, including the oscillation circuits, are stopped and the inter-
nal states in effect before the system was stopped are held with low power consumption.
In the STOP mode, the peripheral circuits stop in the states when the STOP mode is activated or be-
come the same as the states when a reset is released. For operations of the peripheral circuits in the
STOP mode, refer to the section of each peripheral circuit.
The STOP mode is activated by setting SYSCR1<STOP> to "1".
The STOP mode is released by the STOP mode release signals. After the warm-up time has elapsed,
the operation returns to the mode that was active before the STOP mode, and the operation is restarted by
the instruction that follows the STOP mode activation instruction.
RA000
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2012/5/18