TMP89FW24AFG Datasheet, PDF (52/548 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C1 Series

2. CPU Core
2.3 System clock controller
TMP89FW24A
2.3.5.4 Transition of operation modes
Single-clock mode
RESET
IDLE1
mode
IDLE0
mode
SYSCR2<TGHALT>=”1” ^{(Note 2)}
Warm-up that
follows reset
release
SYSCR2<IDLE> = "1"
NORMAL1 mode
External
high-frequency
clock operation
(Note 3)
Internal
high-frequency
clock operation
Warm-up completed
SYSCR1<STOP> = “1”
Reset release
Interrupt
STOP mode release signal
SYSCR2<XTEN> = "0" SYSCR2<XTEN> = "1"
IDLE2
mode
SYSCR2<IDLE> = "1"
NORMAL2 mode
External
high-frequency
clock operation
(Note 3)
Internal
high-frequency
clock operation
SYSCR1<STOP> = “1”
Interrupt
SYSCR2<SYSCK> = "0"
STOP mode release signal
SYSCR2<SYSCK> = "1"
STOP
mode
SLOW2
mode
SLEEP1
mode
SYSCR2<XEN> = "1" or SYSCR2<XEN> = "0" or
SYSCR2<OSCEN> = "1" SYSCR2<OSCEN> = "0"
SYSCR2<IDLE> = "1"
Interrupt
SYSCR1<STOP> =”1”
SLOW1
mode
STOP mode release signal
(Note 2) SYSCR2<TGHALT> = “1”
Dual-clock mode
SLEEP0
mode
Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2
modes are called the SLOW mode; the IDLE0, IDLE1 and IDLE2 modes are called the IDLE mode; and the
SLEEP0 and SLEEP1 are called the SLEEP mode.
Note 2: The mode is released by the falling edge of the source clock selected at TBTCR<TBTCK>.
Note 3: Switching between the internal high-frequency clock and the external high-frequency clock must be done during
the NORMAL1 or NORMAL2 mode. For details, refer to "(1) High-frequency reference clock (fh)".
Figure 2-9 Operation Mode Transition Diagram
2012/5/18
RA000
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