TC55V040AFT-55 Datasheet, PDF (8/11 Pages) Toshiba Semiconductor – 524,288-WORD BY 8-BIT FULL CMOS STATIC RAM

TC55V040AFT-55,-70
Note:
(1)
(2)
(3)
(4)
(5)
R/W remains HIGH for the read cycle.
If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain
at high impedance.
If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will
remain at high impedance.
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
MIN
TYP
V_DH
Data Retention Supply Voltage
1.5

Ta = −40~40°C


V_DH = 3.0 V
I_DDS2
Standby Current
Ta = −40~85°C


V_DH = 3.6 V Ta = −40~85°C


t_CDR
t_R
Chip Deselect to Data Retention Mode Time
Recovery Time
0

t_RC(See ^Note)

Note: Read cycle time
MAX
3.6
1
5
7


UNIT
V
µA
ns
ns
CE1 CONTROLLED DATA RETENTION MODE ^{(See Note 1)}
V_DD
2.7 V
V_DD
DATA RETENTION MODE
V_IH
CE1
GND
(See Note 2)
t_CDR
V_DD − 0.2 V
CE2 CONTROLLED DATA RETENTION MODE ^{(See Note 3)}
V_DD
V_DD
2.7 V
CE2
V_IH
V_IL
GND
t_CDR
DATA RETENTION MODE
0.2 V
(See Note 2)
T_R
t_R
2003-08-06 8/11