TC55V040AFT-55 Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – 524,288-WORD BY 8-BIT FULL CMOS STATIC RAM

TC55V040AFT-55,-70
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V040AFT is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 µA standby
current (at VDD = 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low.
There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and
output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system
applications where high speed, low power and battery backup are required. And, with a guaranteed operating
extreme temperature range of −40° to 85°C, the TC55V040AFT can be used in environments exhibiting extreme
temperature conditions. The TC55V040AFT is available in normal and reverse pinout plastic 40-pin
thin-small-outline package (TSOP).
FEATURES
• Low-power dissipation
Operating: 10.8 mW/MHz (typical)
• Single power supply voltage of 2.3 to 3.6 V
• Power down features using CE1 and CE2
• Data retention supply voltage of 1.5 to 3.6 V
• Direct TTL compatibility for all inputs and outputs
• Wide operating temperature range of −40° to 85°C
• Standby Current (maximum):
3.6 V
3.0 V
7 µA
5 µA
• Access Times (maximum):
TC55V040AFT
-55
-70
Access Time
55 ns
70 ns
CE1 Access Time
55 ns
70 ns
CE2 Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
• Package:
TSOPᶗ40-P-1014-0.50 (AFT) (Weight: 0.32 g typ)
PIN ASSIGNMENT (TOP VIEW)
40 PIN TSOP
1
40
20
21
(Normal)
PIN NAMES
A0~A18
CE1 , CE2
R/W
OE
I/O1~I/O8
V_DD
GND
NC
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
Pin No.
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
Pin Name A16 A15 A14 A13 A12 A11 A9 A8 R/W CE2 NC NC A18 A7 A6 A5 A4 A3 A2 A1
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Name A0 CE1 GND OE I/O1 I/O2 I/O3 I/O4 NC V_DD V_DD I/O5 I/O6 I/O7 I/O8 A10 NC NC GND A17
2003-08-06 1/11