TC551001BPL Datasheet, PDF (8/13 Pages) Toshiba Semiconductor – SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM

TC551001BPL/BFL/BFTL/BTRL-70L/85L
Static RAM
Data Retention Characteristics (Ta = 0 ~ 70°C)
SYMBOL
PARAMETER
V_DH Data Retention Supply Voltage
I_DDS2 Standby Current
t_CDR
t_R
Chip Deselect to Data Retention Mode
Recovery Time
V_DD = 3.0V
V_DD = 5.5V
*3µA (max.) Ta = 0 ~ 40°C
CE1 Controlled Data Retention Mode ⁽¹⁾
MIN. TYP.
2.0
–
–
–
–
–
0
–
5
–
MAX.
5.5
15*
30
–
–
UNIT
V
µA
ns
ms
SR01020795
CE2 Controlled Data Retention Mode ⁽³⁾
Notes:
1. In the CE1 controlled data retention mode, minimum standby current is achieved under the condition CE2 ≤ 0.2V or
CE2 ≥ V_DD - 0.2V.
2. If the V_IH of CE1 is 2.2V in operation, during the period that the V_DD voltage is going down from 4.5V to 2.4V, I_DDS1
current flows.
3. In the CE2 controlled data retention mode, minimum standby current is achieved under the condition CE2 ≤ 0.2V.
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