TC551001BPL Datasheet, PDF (3/13 Pages) Toshiba Semiconductor – SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM

SR01020795
Static RAM
TC551001BPL/BFL/BFTL/BTRL-70L/85L
DC Recommended Operating Conditions
SYMBOL
PARAMETER
V_DD Power Supply Voltage
V_IH Input High Voltage
V_IL Input Low Voltage
V_DH Data Retention Supply Voltage
* -3.0V at pulse width of 50ns Max.
MIN.
4.5
2.2
-0.3*
2.0
TYP. MAX. UNIT
5.0
5.5
–
V_DD + 0.3
V
–
0.8
–
5.5
DC and Operating Characteristics (Ta = 0 ~ 70ºC, V_DD = 5V±10%)
SYMBOL
PARAMETER
TEST CONDITION
MIN. TYP. MAX. UNIT
I_LI Input Leakage Current
I_LO Output Leakage Current
I_OH Output High Current
I_OL Output Low Current
I_DDO1
Operating Current
I_DDO2
I_DDS1
I_DDS2(1) ^{Standby Current}
V_IN = 0 ~ V_DD
–
– ±1.0 µA
CE1 = V_IH or CE2 = V_IL or R/W = V_IL or
OE = V_IH, V_OUT = 0 ~ V_DD
–
– ±1.0 µA
V_OH = 2.4V
-1.0 –
–
mA
V_OL = 0.4V
4.0
–
–
mA
CE1 = V_IL and CE2 = V_IH
Min. –
–
70
and R/W = V_IH,
I_OUT = 0mA
t_cycle
1µs
–
–
20
Other Inputs = V_IH/V_IL
CE1 = 0.2V and
CE2 = V_DD - 0.2V
R/W = V_DD - 0.2V
I_OUT = 0mA
Other Inputs
= V_DD - 0.2V/0.2V
Min. –
–
60
mA
t_cycle
1µs
–
–
10
CE1 = V_IH or CE2 = V_IL
–
–
3
mA
CE1 = V_DD - 0.2V or
CE2 = 0.2V
V_DD = 2.0V ~ 5.5V
Ta = 0 ~ 70°C
–
–
30
Ta = 25°C
µA
–
2
4
Note: (1) In standby mode with CE1 ≥ V_DD - 0.2V, these specification limits are guaranteed under the condition of CE2 ≥ V_DD - 0.2V or CE2 ≤ 0.2V.
Capacitance (Ta = 25ºC, f = 1MHz)
SYMBOL
PARAMETER
TEST CONDITION
C_IN Input Capacitance
C_OUT Output Capacitance
V_IN = GND
V_OUT = GND
Note: This parameter is periodically sampled and is not 100% tested.
MAX.
10
10
UNIT
pF
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
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