TC51WKM616AXBN75 Datasheet, PDF (8/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 4,194,304-WORD BY 16-BIT CMOS PSEUDO STATIC RAM

Deep Power-down Timing
CE1
CE2
Power-on Timing
V_DD
t_CS
V_DD min
TC51WKM616AXBN75
t_DPD
t_CH
CE1
t_CHC
CE2
t_CH
t_CHP
Provisions of Address Skew
Read
In case, multiple invalid address cycles shorter than t_RCmin sustain over 10µs in a active status, as least one
valid address cycle over t_RCmin must be needed during 10µs.
over 10µs
CE1
WE
Address
t_RCmin
Write
In case, multiple invalid address cycles shorter than t_WCmin sustain over 10µs in a active status, as least one
valid address cycle over t_WCmin with t_WPmin must be needed during 10µs.
over 10µs
CE1
t_WPmin
WE
Address
t_WCmin
2002-08-22 8/11