TC51WKM616AXBN75 Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 4,194,304-WORD BY 16-BIT CMOS PSEUDO STATIC RAM

TC51WKM616AXBN75
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4,194,304-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM616AXBN is a 67,108,864-bit pseudo static random access memory(PSRAM) organized as
4,194,304 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.3 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
FEATURES
• Organized as 4,194,304 words by 16 bits
• Dual power supplies(2.6 to 3.3 V for core and
1.7 to 2.2 V for output buffer)
• Direct TTL compatibility for all inputs and outputs
• Deep power-down mode: Memory cell data invalid
• Page operation mode:
Page read operation by 8 words
• Logic compatible with SRAM R/W ( WE ) pin
• Standby current
Standby
100 µA
Deep power-down standby 5 µA
• Access Times:
Access Time
75 ns
CE1 Access Time
75 ns
OE Access Time
25 ns
Page Access Time
30 ns
• Package:
P-TFBGA48-0811-0.75BZ (Weight:
g typ.)
PIN ASSIGNMENT (TOP VIEW)
1
2
3
4
5
6
A LB OE A0 A1 A2 CE2
B I/O9 UB A3 A4 CE1 I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D VSS I/O12 A17 A7 I/O4 VDD
E VDDQ I/O13 A21 A16 I/O5 VSS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 A19 A12 A13 WE I/O8
H A18 A8 A9 A10 A11 A20
(FBGA48)
PIN NAMES
A0 to A21 Address Inputs
A0 to A2 Page Address Inputs
I/O1 to I/O16 Data Inputs/Outputs
CE1
Chip Enable Input
CE2
Chip select Input
WE
Write Enable Input
OE
Output Enable Input
LB , UB Data Byte Control Inputs
V_DD
V_DDQ
GND
Power Supply for Core
Power Supply for Output Buffer
Ground
2002-08-22 1/11