TMPR4937 Datasheet, PDF (71/552 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 4 Address Mapping
4.2.3
Register Map
Please refer to “10.5 PCI Configuration Space Register” about PCI configuration register.
Table 4.2.2 Register Map
Offset Address
Peripheral Controller
0x0000 to 0x7FFF
0x8000 to 0x8FFF
0x9000 to 0x9FFF
0xA000 to 0xAFFF
0xB000 to 0xB7FF
0xB800 to 0xBFFF
0xD000 to 0xDFFF
0xE000 to 0xEFFF
0xF000 to 0xF0FF
0xF100 to 0xF1FF
0xF200 to 0xF2FF
0xF300 to 0xF3FF
0xF400 to 0xF4FF
0xF500 to 0xF50F
0xF510 to 0xF6FF
0xF700 to 0xF7FF
0xF800 to 0xFFFF
Reserved
SDRAMC
EBUSC
ECC
DMAC0
DMAC1
PCIC
CONFIG
TMR0
TMR1
TMR2
SIO0
SIO1
PIO
IRC
ACLC
Reserved
Detail
⎯
Refer to “9.4”
Refer to “7.4”
Refer to “9.4”
Refer to “8.4”
Refer to “8.4”
Refer to “10.4”
Refer to “5.2”
Refer to “12.4”
Refer to “12.4”
Refer to “12.4”
Refer to “11.4”
Refer to “11.4”
Refer to “13.4”
Refer to “15.4”
Refer to “14.4”
4-3