TMPR4937 Datasheet, PDF (115/552 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 7 External Bus Controller
7.3.7.3
ACK* Output Timing (Normal Mode, Page Mode)
When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK*
signal becomes an output signal and is asserted for one clock cycle to send notification to the
external device of the data Read and data Write timing.
During the Read cycle, the data is latched at the rise of the next clock cycle after when the
ACK* signal is asserted. (See Figure 7.3.7 ACK* Output Timing (Single Read Cycle)).
During the Write cycle, SWE*/BWE* is deasserted at the next clock cycle after when the ACK*
signal is deasserted, and the data is held for one more clock cycle after that. (See Figure 7.3.8
ACK* Output Timing (Single Write Cycle)).
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY
(Output)
1 clock
Data is latched
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
Figure 7.3.7 ACK* Output Timing (Single Read Cycle)
SYSCLK
CE*
ADDR [19:0]
SWE*/BWE*
DATA [31:0]
ACK*/READY
(Output)
2 clocks
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
Figure 7.3.8 ACK* Output Timing (Single Write Cycle)
7-15