TMPR4937 Datasheet, PDF (329/552 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 10 PCI Controller
10.4.43 PCI Controller Configuration Register (PCICCFG) 0xD170
31
28 27
Reserved
GBWC
R/W
0xfff
16
: Type
: Initial value
15
12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
HRST SRST IRBER G2PM0EN G2PM1EN G2PM2EN G2PIOEN TCAR ICAEN LCFG Reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0
: Type
: Initial value
Bit Mnemonic Field Name
31:28
Reserved
27:16
GBWC
G-Bus Wait
Counter Setting
15:12
11
HRST
Reserved
Hardware Reset
Description
Read/Write
⎯
G Bus Wait Counter (Default: 0xFFF)
R/W
Sets the Retry response counter at the G-Bus during a PCI initiator Read
transaction.
When the initiator Read access cycle exceeds the setting of this counter, a
Retry response is sent to the G-Bus and the G-Bus is released. PCI Read
operation continues. This counter uses the G-Bus clock (GBUSCLK) when
operating.
When 0x000 is set, a Retry response is not sent to the G-Bus by a long
response cycle count.
When the G-Bus timeout count is used with the value other than the initial
value 4096 GBUSCLK, G-BUS timeout may occur before a Retry response
is sent.
When G-Bus timeout of the configuration register (CCFG.GTOT) is used
with the value other than the initial value (11), set the following maximum
values to the register.
GTOT value
Maximum value of the register
10 (2048 GBUSCLK) : 0x7f0
01 (1024 GBUSCLK) : 0x3f0
00 ( 512 GBUSCLK) : 0x1f0
⎯
Hard Reset (Default: 0x0)
R/W
Performs PCI Controller hardware reset control. EEPROM reloading is also
performed. This bit is automatically cleared when Reset ends. This is a
diagnostic function.
The PCI Controller cannot be accessed for 32 G-Bus clock cycles after this
bit is set.
1: Perform a hardware reset on the PCI Controller.
0: Do not perform a hardware reset on the PCI Controller.
Figure 10.4.41 PCI Controller Configuration Register (1/3)
10-71