TMPR4937 Datasheet, PDF (347/552 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 10 PCI Controller
10.4.58 PDMAC Chain Address Register (PDMCA)
63
Reserved
47
Reserved
31
PDMCA[31:16]
R/W
Undefined
15
PDMCA[15:3]
R/W
Undefined
0xD200
48
: Type
: Initial value
36 35
32
PDMCA[35:32]
R/W
undefined
: Type
: Initial value
16
: Type
: Initial value
3
2
0
Reserved
: Type
: Initial value
Bits Mnemonic Field Name
63:36
Reserved
35:3 PDMCA Chain Address
2:0
Reserved
Description
Read/Write
⎯
PDMAC Chain Address (Default is undefined)
The address of the next PDMAC Data Command Descriptor to be read is
specified by a G-Bus physical address on a 64-bit address boundary. This
register value is held without being affected by a Reset.
0 value judgement is performed when the lower 32 bits of this register are
rewritten. DMA transfer is automatically initiated if the result is not “0”.
R/W
⎯
Figure 10.4.56 PDMAC Chain Address Register
10-89