TA1276AFG Datasheet, PDF (70/83 Pages) Toshiba Semiconductor – PAL/NTSC Video Chroma And Deflection IC For CTV

TA1276AFG
Note
Parameter
SW₁₆
Test Conditions (unless otherwise stated, V_CC1 = 5 V, V_CC2/V_CC3/DEF V_CC = 9 V, Ta = 25 ± 3°C)
Switching Mode
SW₁₇ SW₁₈ SW₂₀ SW₂₃ SW₂₅
Test Conditions
52
˓^M
Pin 52
TP52
TG7
(sync input)
Apply a 50 Hz composite video signal to TP52, then
measure the phase difference VP_50S1 and the pulse
width VP_50S2 of the pin 70 (SCP) waveform in relation to
the pin 49 (sync input) waveform.
Vertical Blanking Pulse Start
Phase (1)
D₉
D
Vertical Blanking Pulse End
Phase (1)
C
ON ON
A
ON ⁴⁷
70
Pin 47
(sync input)
Pin 70
(SCP)
Vertical Blanking Pulse Start
Phase (2)
D₁₀
Vertical Blanking Pulse End
↑
↑
↑
↑
↑
↑
Apply the same conditions as those for D₉ except change the input signal to a 60 Hz comp. video signal
and measure the phase difference VP_60S and pulse width VP_60W.
Phase (2)
Vertical Pull-In Range (1)
Input a 50 Hz composite video signal to pin TP52, vary the vertical frequency of this signal in 0.5H-steps,
and measure the vertical pull-in range.
Vertical Pull-In Range (2)
Set D₅ to D₃ of subaddress (17) to (001), vary the vertical frequency of a 60 Hz composite video signal
input to pin TP52 in 0.5H-steps, and measure the vertical pull-in range.
D_{11 Vertical Pull-In Range (3)}
Input a 50 Hz composite video signal to pin TP52, vary the vertical frequency of this signal in 0.5H-steps,
↑
↑
↑
↑
↑
↑ and measure the number of Hs when D2 of the 1^st byte changes from 0 to 1 in bus read mode. Also check
that D₁ of the 1^st byte is 0 when 1 V = 312.5H, when D₁ is 1 in bus read mode, and 1 V < 311.5 or 1 V >
313.5H.
Vertical Pull-In Range (4)
Input a 60 Hz composite video signal to pin TP52, vary the vertical frequency of this signal in 0.5H-steps,
and measure the number of Hs when D₂ of the 1^st byte changes from 1 to 0 in bus read mode when. Also
check that D₁ of the 1^st byte is 0 when 1 V = 262.5H, D₁ is 1 in bus read mode, and 1 V < 261.5 or 1 V >
263.5H.
70
2002-04-01