TC9WMA1FK Datasheet, PDF (7/12 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic

TC9WMA1FK
Electrical Characteristics
D.C. Characteristics (GND = 0 V, V_CC = 2.7~3.6 V, T_opr = -40~85°C)
Characteristics
Input current
Output leakage current
High level output voltage
Low level output voltage
Quiescent supply current
Supply current during read
Supply current during all
erase/program
Symbol
Test Condition
I_LI
I_LO
V_OH
V_CC = 2.7 V, I_OH = -1 mA
V_OL
V_CC = 2.7 V, I_OL = 2 mA
I_CC1 (Note1)
I_CC2 (Note2)
I_CC3 (Note3)
Min Typ. Max Unit
¾
¾
±5
mA
¾
¾
±5
mA
V_CC -
0.4
¾
¾
V
¾
¾
0.4
V
¾¾
5
mA
¾
¾
1.5 mA
¾
¾
1.0 mA
Note 1: CS = 1 (except when busy, however)
Note 2: Current that flows for a period from a fall of the 14th to a fall of the 17th CLK pulse when executing the
read instruction.
Note 3: Current that flows while executing the all erase or program instruction.
A.C. Characteristics (GND = 0 V, V_CC = 2.7~3.6 V, T_opr = -40~85°C)
Characteristics
Symbol
Test Condition
Min
Maximum clock frequency
Minimum clock pulse width
Minimum reset pulse width
Minimum chip select pulse width
Reset setup time
Clock setup time
CS setup time
Propagation delay time
(Note4)
Input data setup time
Input data hold time
f_MAX
0
twCLK (L)
400
twCLK (H)
t_WRST
1
t_WCS
1
t_RSS
RST setup time when CS is
switched over
1
t_CKS
CLK setup time when CS is switched
over
250
t_CSS
CS setup time when CLK is
switched over
250
t_pLH
t_pHL
t_pZH
Time from CLK switchover until valid
data is output
¾
t_pZL
t_pLZ
t_pHZ
Time from CS switchover until output
data goes Hi-Z
¾
t_s
Input data setup time when CLK is
switched over
250
t_h
Input data hold time when CLK is
switched over
250
Note 4: C_L = 100 pF, R_L = 1 kW
Max Unit
1
MHz
¾
ns
¾
ms
¾
ms
¾
ms
¾
ns
¾
ns
250
ns
500
¾
ns
¾
ns
7
2001-10-16