TC9WMA1FK Datasheet, PDF (3/12 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic

TC9WMA1FK
Functional Description
1. Types of Instructions
Operation
Read
Program
All erase
Busy monitor
Overwrite enable
Overwrite disable
*: Don’t care
Address
A0~A6, 0
A0~A6, 0
********
********
********
********
Command
C0 C1 C2 C3
1000
0000
0110
0000
0011
0000
1011
0000
1001
0000
1101
0000
Data
D0~D7
2. Operation Method
Be sure to return CS and CLK high temporarily before entering instructions.
After CS is asserted low, CLK becomes effective, acting as a serial transfer synchronizing signal. The
data on DI is latched by a rising edge of CLK , while data is output to DO by a falling edge of CLK .
Instructions can only be executed when the chip is not being programmed or collectively erased (i.e., when
the ready/busy status signal is high). However, the Busy Monitor instruction can be entered at any time.
Only the commands listed in the above table can be used. Do not use any other command.
(1) Read
When the Read instruction is entered, memory data at the specified address is read out and is
serially output from the DO pin.
(2) Program
When the Program instruction is entered, overwrite operation automatically starts internally in the
chip, and memory data at the specified address is overwritten with the input data. After the
instruction is entered, CS can be returned high even while overwrite operation is in progress
internally.
(3) All Erase
When the All Erase instruction is entered, erase operation automatically starts internally in the
chip, and memory data at all addresses are erased. After the instruction is entered, CS can be
returned high even while erase operation is in progress internally. Execution of this command clears
the memory data to 0.
(4) Busy Monitor
When the Busy Monitor instruction is entered, a ready/busy status signal is output from the DO pin.
This output signal is low while the chip is being programmed or collectively erased, and is high after
programming or collective erase operation is completed.
The ready/busy status signal is output continuously until CS is returned high.
(5) Overwrite Enable/Disable
When the Overwrite Enable instruction is entered, the chip is placed in overwrite enable mode,
where the Program and All Erase instructions are enabled. When the Overwrite Disable instruction is
entered, the chip is placed in overwrite disable mode, where the Program and All Erase instructions
both are disabled.
Once the chip is placed in overwrite disable mode, it remains disabled against overwriting unless
the Overwrite Enable instruction is entered.
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2001-10-16