TC9444F Datasheet, PDF (7/28 Pages) Toshiba Semiconductor – Single-Chip karaoke IC II

a) (IBIT3, IBIT2, IBIT1) = (0, 0, 0): MSB first, Right-Justified mode, 16-bit data
LRCKI
BCKI
LSB
SDI
0
MSB
LSB
15
0
MSB
15
b) (IBIT3, IBIT2, IBIT1) = (0, 0, 1): MSB first, Right-Justified mode, 18-bit data
LRCKI
BCKI
LSB
MSB
LSB
SDI
0
17
0
MSB
17
c) (IBIT3, IBIT2, IBIT1) = (0, 1, 0): MSB first, Right-Justified mode, 20-bit data
LRCKI
BCKI
LSB
MSB
LSB
SDI
0
19
0
MSB
19
d) (IBIT3, IBIT2, IBIT1) = (0, 1, 1): MSB first, Right-Justified mode, 24-bit data
LRCKI
BCKI
LSB
MSB
LSB
SDI
0
23
0
MSB
23
e) (IBIT3, IBIT2, IBIT1) = (1, 0, 0): IIS-compatible, 24 bits max
LRCKI
BCKI
MSB
LSB
MSB
LSB
SDI
23
0
23
0
Note 3: In either mode, sections where “SDI” is omitted are don’t care (no internal data loading).
Figure 2.1 Data Input Formats (BCK = 64 fs)
The microcontroller interface RLS bit controls the polarity of the input/output channel clock (LRCKI, LRCKO).
Table 2.3 Channel Clock Polarity
RLS
Operation
0
L-channel data input/output when LRCKI and LRCKO =
“H”
1
L-channel data input/output when LRCKI and LRCKO =
“L”
LSB
0
LSB
0
LSB
0
LSB
0
MSB
23
TC9444F
7
2002-01-11