TC9444F Datasheet, PDF (21/28 Pages) Toshiba Semiconductor – Single-Chip karaoke IC II

TC9444F
6. Reset Timing
After turning on the power supply, always perform a reset by setting the /RESET pin to Low.
Figure 6.1 shows the reset and boot timing.
When performing a power-on reset, note the timing shown in Figure 6.2.
RESET
t_Rw > 0.2 ms
t_BOOT < 50 ms
Boot operation completed. Do not write to
the coefficient or offset RAM until boot is
complete.
Figure 6.1 Reset and Boot
V_DD
80%
RESET
40%
t_RST > 1 ms
Figure 6.2 Power-On Reset Timing
7. Microcontroller Interface Signal Timing
Microcontroller interface signal timing supports three-lead mode and I²C bus mode.
7.1 Three-Lead Bus Mode
Setting IFSEL = “H” sets the microcontroller interface to three-lead bus mode.
Setting the CS signal = “L” enables control from the microcontroller.
Figure 7.1 shows the interface timing when three-lead mode is selected.
When transmitting two or more commands, be sure to set CS to H between each command.
When writing to coefficient or offset RAM, be sure to write the data word by word in 1 fs per word.
As coefficient or offset RAM cannot be updated in multiple-word batches, take particular care when
updating filter coefficients.
7.2 I²C Bus Mode
Setting IFSEL = “L” sets the microcontroller interface to I²C bus mode.
In I²C bus mode, the CS pin can be fixed to “L”. Note that the CS pin signal can also be used as
the chip select signal.
The I²C slave address is:
MSB
LSB
1101
1000
^^^^^^^^^^^^^
Data can only be written to this address. Therefore, fix the LSB of read/write mode bits to 0.
As I²C bus mode does not permit continuous writing, insert an END condition after each command,
then a START condition to start writing data again.
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2002-01-11