TC9444F Datasheet, PDF (5/28 Pages) Toshiba Semiconductor – Single-Chip karaoke IC II

Block Operations
TC9444F
1. Operating Clocks
The master clock can be selected between 512 or 384 fs using the CKS pin. The master clock uses
oscillator or external clock input, through the XI pin.
Regardless of a master clock, the number of digital signal processing steps are predetermined. However,
the DA converter’s operating clock varies according to the master clock mode.
The MCKS pin sets the MCKO output, selecting 1/1 or 1/2 divider of the XI pin.
Table 1.1 Operating Clock Selection and DA Converter Oversampling Rate
CKS Pin
L
H
MCKS Pin
L
H
L
H
XI Input
384 fs
512 fs
MCKO Output
192 fs
384 fs
256 fs
512 fs
DAC Oversampling Rate
192 fs
256 fs
2. Digital Audio Data Input/Output
2.1 Sync Mode
The data input/output bit clock and internal sync (master) mode or external sync (slave) mode are
set using microcontroller interface bits SYNM1 and SYNM2. Initialization by reset sets master mode.
Table 2.1 Sync Mode and Input/Output Bit Clock Settings
SYNM2
SYNM1 SYNC Mode
0
0
Master
0
1
Slave
1
0
Slave
1
1
Slave
Note 1: See Table 2.2.
Note 2: XI input divider clock
BCKI
(Note 1)
32 fs
48 fs
64 fs
BCKO
64 fs
(Note 2)
BCKI
BCKI
BCKI
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2002-01-11