TC5565APL Datasheet, PDF (7/9 Pages) Toshiba Semiconductor – 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology

TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 1. R/W is High for Read Cycle.
2. Assuming that \CE1 Low transition of CE2 High transition occurs coincident with or after R/W Low transition, Outputs
remain in a high impedance state.
3. Assuming that \CEl High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, Outputs
remain in a high impedance state.
4. Assuming that \OE is High for Write Cycle, Outputs are in high impedance state during this period.
DATA RETENTION CHARACTERISTICS (Ta=0~70°C)
SYMBOL
PARAMETER
V_DH
I_DDS2
Data Retention Supply Voltage
Stand by Supply Current
VDD=3.0V
VDD=5.5V
t_CDR
Chip Deselection to Data Retention Mode
t_R
Recovery Mode
Note (1) : Read cycle Time.
MIN.
2.0
-
-
0
tRC(1)
TYP.
-
-
-
-
-
MAX.
5.5
50
100
-
-
UNIT
V
uA
us
us
\CE1 Controlled Data Retention Mode (2)
CE2 Controlled Data Retention Mode (4)