TC5565APL Datasheet, PDF (3/9 Pages) Toshiba Semiconductor – 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology

TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
D.C and OPERATING CHARACTERISTICS (Ta=0~70°C, V_DD = 5V±10%)
SYMBOL
PARAMETER
TEST CONDITION
MIN. TYP. MAX. UNIT
I_IL
Input Leakage
Current
V_IN=O~V_DD
- - ±1.0 uA
I_OH
I_OL
I_LO
Output High Current VOH-2-4V
Output Low Current VOL-0.4V
Output Leakage Current
V_IH or CE2-VOL or
\CE1 = V_IH or CE2=V_OL 0r R/W = V_IL
or \OE=V_IH
V_OUT=0~V_DD
t_cycle =1.0us
-1.0 -
mA
4.0 -
mA
- - ±1.0 uA
10 mA
TC5565APL-10 t_cycle
TC556SAFL-10 =100ns
- - 45 mA
I_DDO1
V_DD =5.5V
\CE1=V_IL
CE2=V_IH
Other input=
V_IH/V_IL
TC5565APL-12 t_cycle
TC5565AFL-12 =120ns
- - 40 mA
Operating Current
I_DD02
TC5565A?L-15 t_cycle
TC5565AFL-15 =150ns
- - 35 mA
t_cycle=1.0us
- - 5 mA
TC5565APL-10
t_cycle =100ns - - 40 mA
V_DD=5.5V
TC5565AFL-10
\CEl=O.2V
CE2=V_DD –0.2V TC5565AFL-12
Other lnput=
t_cycle =120ns
-
-
35 mA
V_DD - 0.2V/0.2V ^TC5565AFL-12
TC5565APL-15
TC5565AFL-15 ^{tcycle =150ns}
-
-
30 mA
I_DDS1
*I_DDS2
Standby Current
\Cel = V_IH or CE2 = V_IL
\CE1 = V_DD – 0.2V or
CE2 = 0.2V
V_DD = 5.5V
V_DD = 3.0V
3 mA
- 2 100 uA
- 1 50 uA
Note * In standby mode with \CE1>= V_DD – 0.2V, these specification limits are guaranteed under the condition of
CE2 >= V_DD – 0.2V or CE2 <= 0.2V.
CAPACITANCE (Ta=25°C)
SYMBOL
PARAMETER
C_IN
Input Capacitance
C_OUT
Output Capacitance
* This parameter periodically sampled is not 100% tested.
TEST CONDITION
V_IN = GND
V_OUT = GND
MIN. TYP.
-
-
-
-
MAX. UNIT
10
pF
10
pF