TC5565APL Datasheet, PDF (4/9 Pages) Toshiba Semiconductor – 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology

TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
A.C. CHARACTERISTICS (Ta=0~70°C, V_DD = 5V±10%)
Read Cycle
SYMBOL PARAMETER
t_RC
Read Cycle Time
t_ACC
Address Access Time
t_COL
\CE1 Access Time
t_C02
CE2 Access Time
t_OE
Output Enable to Output Valid
t_COE
Chip Enable (\CE1, CE2) to
Output in Low-Z
t_OEE
Output Enable to Output in Low-Z
t_OD
Chip Enable (CE1, CE2) to
Output in High-Z
t_ODO
Output Enable to Output in High-Z
t_OH
Output Data Hold Time
TC5565APL-10
TC5565AFL-10
MIN. MAX.
100
-
-
100
-
100
-
100
-
50
10
-
5
-
-
35
-
35
20
-
TC5565APL-12 TC5565APL-15
TC5565AFL-12 TC5565AFL-15
MIN. MAX. MIN. MAX
120
-
150
-
-
120
-
150
-
120
-
150
-
120
-
150
-
60
-
70
10
-
15
-
5
-
5
-
-
40
-
50
-
40
-
50
20
-
20
-
Write Cycle
SYMBOL
PARAMETER
t_WC
Write Cycle Time
t_WP
Write Pulse Width
t_CW
Chip Selection to End of Write
t_AS
Address Set up Time
r_WR
Write Recovery Time
t_ODW
R/W to Output High-Z
r_OEW
R/W to Output Low-Z
t_DS
Data Set up Time
t_DH
Data Hold Time
A.C. TEST CONDITION
TC5565APL-10
TC5565AFL-10
MIN. MAX.
100
-
60
-
80
-
0
-
0
-
-
35
5
-
40
-
0
-
TC5565APL-12 TC5565APL- 5
TC5565AFL-12 TC5565AFL- 5
MIN. MAX. MIN. MAX..
120
-
150
-
70
-
90
-
85
-
100
-
0
-
0
-
0
-
0
-
0
40
-
50
5
-
10
-
50
-
60
-
0
-
0
-
Output Load
Input Pulse Level
Timing Measurement
Reference Level
t_r, t_f
V_IN
V_OUT
: 100pF + 1 TTL Gate
: 0.6V, 2.4V
: 0.8V, 2.2V
: 0.8V, 2.2V
: 5ns