TMP89FM42 Datasheet, PDF (61/408 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP89FM42
3. Interrupt Control Circuit
The TMP89FM42 has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Three
of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vec-
tor addresses. When a request for an interrupt is generated, its interrupt latch is set to "1", which requests the CPU to
accept the interrupt. Acceptance of interrupts is enabled or disabled by software using the interrupt master enable
flag (IMF) and individual enable flag (EF) for each interrupt source. If multiple maskable interrupts are generated
simultaneously, the interrupts are accepted in order of descending priority. The priorities are determined by the inter-
rupt priority change control register (ILPRS1-ILPRS6) as Levels and determined by the hardware as the basic prior-
ities.
However, there are no prioritized interrupt sources among non-maskable interrupts.
Interrupt sources
Internal/
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
External
External
External
External
Internal
Internal
Internal
Internal
Internal
-
-
(Reset)
INTSWI
INTUNDEF
INTWDT
INTWUC
INTTBT
INTRXD0 / INTSIO0
INTTXD0
INT5
INTVLTD
INTADC
INTRTC
INTTC00
INTTC01
INTTCA0
INTSBI0/INTSIO0
INT0
INT1
INT2
INT3
INT4
INTTCA1
INTRXD1
INTTXD1
INTTC02
INTTC03
-
-
Enable condition
Interrupt
latch
Vector Address
(MCU mode)
RVCTR=0 RVCTR=1
enabled enabled
Basic
prior-
ity
Non-maskable
-
0xFFFE
-
1
Non-maskable
-
0xFFFC 0x01FC
2
Non-maskable
-
0xFFFC 0x01FC
2
Non-maskable
ILL<IL3> 0xFFF8
0x01F8
2
IMF AND EIRL<EF4> = 1
ILL<IL4> 0xFFF6
0x01F6
5
IMF AND EIRL<EF5> = 1
ILL<IL5> 0xFFF4
0x01F4
6
IMF AND EIRL<EF6> = 1
ILL<IL6> 0xFFF2
0x01F2
7
IMF AND EIRL<EF7> = 1
ILL<IL7> 0xFFF0
0x01F0
8
IMF AND EIRH<EF8> = 1
ILH<IL8> 0xFFEE 0x01EE
9
IMF AND EIRH<EF9> = 1
ILH<IL9> 0xFFEC 0x01EC
10
IMF AND EIRH<EF10> = 1 ILH<IL10> 0xFFEA 0x01EA
11
IMF AND EIRH<EF11> = 1 ILH<IL11> 0xFFE8
0x01E8
12
IMF AND EIRH<EF12> = 1 ILH<IL12> 0xFFE6
0x01E6
13
IMF AND EIRH<EF13> = 1 ILH<IL13> 0xFFE4
0x01E4
14
IMF AND EIRH<EF14> = 1 ILH<IL14> 0xFFE2
0x01E2
15
IMF AND EIRH<EF15> = 1 ILH<IL15> 0xFFE0
0x01E0
16
IMF AND EIRE<EF16> = 1 ILE<IL16> 0xFFDE 0x01DE
17
IMF AND EIRE<EF17> = 1 ILE<IL17> 0xFFDC 0x01DC
18
IMF AND EIRE<EF18> = 1 ILE<IL18> 0xFFDA 0x01DA
19
IMF AND EIRE<EF19> = 1 ILE<IL19> 0xFFD8
0x01D8
20
IMF AND EIRE<EF20> = 1 ILE<IL20> 0xFFD6
0x01D6
21
IMF AND EIRE<EF21> = 1 ILE<IL21> 0xFFD4
0x01D4
22
IMF AND EIRE<EF22> = 1 ILE<IL22> 0xFFD2
0x01D2
23
IMF AND EIRE<EF23> = 1 ILE<IL23> 0xFFD0
0x01D0
24
IMF AND EIRD<EF24> = 1 ILD<IL24> 0xFFCE 0x01CE
25
IMF AND EIRD<EF25> = 1 ILD<IL25> 0xFFCC 0x01CC
26
-
-
-
-
-
-
-
-
-
-
Note 1: To use the watchdog timer interrupt (INTWDT), clear WDCTR<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 2: 0xFFFA and 0xFFFB function not as interrupt vectors but as option codes in the serial PROM mode. For details, see
"Serial PROM Mode".
Note 3: Vector address areas can be changed by the SYSCR3<RVCTR> setting. To assign vector address areas to RAM, set
SYSCR3<RVCTR> to "1" and SYSCR3<RAREA> to "1".
RA003
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