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TMP89FM42 Datasheet, PDF (190/408 Pages) Toshiba Semiconductor – 8 Bit Microcontroller
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14. 8-bit Timer Counter (TC0)
TMP89FM42
If the value set to T00REG is smaller than the up counter value, the match detection is exe-
cuted using a new set value after the up counter overflows. Therefore, the interrupt request
interval may be longer than the selected time. If the value set to T00REG is equal to the up
counter value, the match detection is executed immediately after data is written into T00REG.
Therefore, the interrupt request interval may not be an integral multiple of the source clock
(Figure 14-3). If these are problems, enable the double buffer.
When a write instruction is executed on T00REG while the timer is stopped, the set value is
immediately stored in T00REG.
When a read instruction is executed on T00REG, the last value written into T00REG is read out, regard-
less of the T00MOD<DBE0> setting.
Table 14-5 8-bit Timer Mode Resolution and Maximum Time Setting
T00MOD
<TCK0>
000
001
010
011
100
101
110
111
Source clock [Hz]
NORMAL1/2 or IDLE1/2 mode
SYSCR1<DV9CK> SYSCR1<DV9CK>
= "0"
= "1"
fcgck/211
fs/24
fcgck/210
fs/23
fcgck/28
fcgck/28
fcgck/26
fcgck/26
fcgck/24
fcgck/24
fcgck/22
fcgck/22
fcgck/2
fcgck/2
fcgck
fcgck
SLOW1/2 or
SLEEP1 mode
fs/24
fs/23
-
-
-
-
-
fs/22
Resolution
Maximum time setting
fcgck=10MHz fs=32.768KHz fcgck=10MHz fs=32.768KHz
204.8µs
102.4µs
25.6µs
6.4µs
1.6µs
400ns
200ns
100ns
488.2µs
244.1µs
-
-
-
-
-
122.1µs
52.2ms
26.1ms
6.5ms
1.6ms
408µs
102µs
51µs
25.5µs
124.5ms
62.3ms
-
-
-
-
-
31.1ms
(Example) Operate TC00 in the 8-bit timer mode with the operation clock of fcgck/22 [Hz] and generate interrupts at 64 µs intervals
(fcgck = 10 MHz)
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
LD
(T00MOD),0xE8
LD
(T00REG),0xA0
SET
(T001CR).0
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 8-bit timer mode and fcgck/22
; Sets the timer register (64µs / (22/fcgck) = 0xA0)
; Starts TC00
RA002
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