TMP89FM42 Datasheet, PDF (318/408 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

21. Flash Memory
TMP89FM42
21.1 Flash Memory Control
The flash memory is controlled by the flash memory control register 1 (FLSCR1), flash memory control register 2
(FLSCR2), and flash memory standby control register (FLSSTB).
Flash memory control register 1
FLSCR1
7
6
5
4
3
2
(0x0FD0)
Bit Symbol
FLSMD
BAREA
FAREA
Read/Write
R/W
R/W
R/W
After reset
0
1
0
0
0
0
1
0
-
-
R/W
R/W
0
0
FLSMD
BAREA
FAREA
Flash memory command
sequence and toggle control
BOOTROM mapping control
Flash memory area select control
010: Disable command sequence and toggle execution
101: Enable command sequence and toggle execution
Others: Reserved
MCU mode
Serial PROM mode
0: Hide BOOTROM
1: Show BOOTROM
-
Show BOOTROM
00: Assign the data area 0x8000 through 0xFFFF
to the data area 0x8000 through 0xFFFF (standard mapping).
01: Reserved
10: Assign the code area 0x8000 through 0xFFFF
to the data area 0x8000 through 0xFFFF.
11: Reserved
Note 1:
Note 2:
Note 3:
It is prohibited to make a setting in "Reserved".
The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.
Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This
means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift
register can be checked by reading the register FLSCRM.
FLSMD must be set to either "0y010" or "0y101".
Flash memory control register 2
FLSCR2
7
6
5
4
3
2
1
0
(0x0FD1)
Bit Symbol
CR1EN
Read/Write
W
After reset
*
*
*
*
*
*
*
*
CR1EN
FLSCR1 register
enable/disable control
0xD5 Enable a change in the FLSCR1 setting
Others Reserved
Note 1: If "0xD5" is set on FLSCR2<CR1EN> with FLSCR1<FLSMD> set to "101", the flash memory goes into an active state,
and MCU consumes the same amount of current as it does during a read.
RA003
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