TMP89FM42 Datasheet, PDF (30/408 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

2. CPU Core
2.3 System clock controller
TMP89FM42
Note 3: If the STOP mode is activated with SYSCR1<OUTEN> set at "0", the port internal input is fixed to "0". Therefore, an exter-
nal interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated.
Note 4: The P11 pin is also used as the STOP pin. When the STOP mode is activated, the pin reverts to high impedance state and
is put in input mode, regardless of the state of SYSCR1<OUTEN>.
Note 5: Writing of the second byte data will be executed improperly if the operation is switched to the STOP state by an instruc-
tion, such as LDW, which executes 2-byte data transfer at a time.
Note 6: Don't set SYSCK1<DV9CK> to "1" before the oscillation of the low-frequency clock oscillation circuit becomes stable.
Note 7: In the SLOW1/2 or SLEEP1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of SYSCR1< DV9CK >.
System control register 2
SYSCR2
7
6
5
4
3
2
1
0
(0x0FDD)
Bit Symbol
-
XEN
XTEN
SYSCK
IDLE
TGHALT
-
-
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R
R
After reset
0
1
0
0
0
0
0
0
XEN
XTEN
Controls the high-frequency clock
oscillation circuit
Controls the low-frequency clock
oscillation circuit
SYSCK Selects a system clock
IDLE
CPU and WDT control
(IDLE1/2 or SLEEP1 mode)
TG control
TGHALT
(IDLE0 or SLEEP0 mode)
0 : Stop oscillation
1 : Continue or start oscillation
0 : Stop oscillation
1 : Continue or start oscillation
0 : Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode)
1 : Low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode)
0 : Operate the CPU and the WDT
1 : Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode)
0 : Enable the clock supply from the TG to all the peripheral circuits
1 : Disable the clock supply from the TG to the peripheral circuits except the
TBT (Activate IDLE0 or SLEEP0 mode)
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: WDT: Watchdog timer, TG: Timing generator
Note 3: Don't set both SYSCR2<IDLE> and SYSCR2<TGHALT> to "1" simultaneously.
Note 4: Writing of the second byte data will be executed improperly if the operation is switched to the IDLE state by an instruction,
such as LDW, which executes 2-byte data transfer at a time.
Note 5: When the IDLE1/2 or SLEEP1 mode is released, SYSCR2<IDLE> is cleared to "0" automatically.
Note 6: When the IDLE0 or SLEEP0 mode is released, SYSCR2<TGHALT> is cleared to "0" automatically.
Note 7: Bits 7, 1 and 0 of SYSCR2 are read as "0".
Warm-up counter control register
WUCCR
7
6
5
4
3
2
1
0
(0x0FCD)
Bit Symbol
WUCRST
-
-
-
WUCDIV
WUCSEL
-
Read/Write
W
R
R
R
R/W
R/W
R
After reset
0
0
0
0
1
1
0
1
WUCRST
WUCDIV
WUCSEL
Resets and stops the warm-up
counter
0: -
1 : Clear and stop the counter
Selects the frequency division of the
warm-up counter source clock
00 : ^{Source clock}
01 : ^{Source clock / 2}
10 : Source clock / 2²
11 : _{Source clock / 2}3
Selects the warm-up counter
source clock
0 : Select the high-frequency clock (fc)
1 : Select the low-frequency clock (fs)
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: WUCCR<WUCRST> is cleared to "0" automatically, and need not be cleared to "0" after being set to "1".
Note 3: Bits 7 to 4 of WUCCR are read as "0". Bit 0 is read as "1".
Note 4: Before starting the warm-up counter operation, set the source clock and the frequency division rate at WUCCR and set
the warm-up time at WUCDR.
RA001
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