TC55V16256JI Datasheet, PDF (6/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TIMING DIAGRAMS
READ CYCLE ^{(See Note 2)}
TC55V16256JI/FTI-12,-15
Address
CE
OE
UB , LB
D_OUT
t_RC
t_ACC
t_CO
t_OE
t_OH
t_COD ^{(See Note 6)}
t_BA
t_ODO ^{(See Note 6)}
t_BE ^{(See Note 6)}
Hi-Z
t_OEE ^{(See Note 6)}
t_COE ^{(See Note 6)}
INDETERMINATE
t_BD ^{(See Note 6)}
VALID DATA OUT
Hi-Z
INDETERMINATE
WRITE CYCLE 1 ( WE CONTROLLED) ^{(See Note 5)}
Address
WE
CE
UB , LB
D_OUT
D_IN
t_WC
t_AW
t_AS
t_WP
t_WR
t_CW
(See Note 3)
INDETERMINATE
t_BW
t_ODW ^{(See Note 6)}
t_OEW ^{(See Note 6)}
Hi-Z
t_DS
t_DH
(See Note 4)
INDETERMINATE
VALID DATA IN
2002-01-07 6/11