TC55V16256JI Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55V16256JI/FTI-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144
words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper
byte access. This device is well suited to cache memory applications where high-speed access and high-speed
storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V16256JI/FTI is available in
plastic 44-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V16256JI/FTI
guarantees −40° to 85°C operating temperature so it is suitable for use in wide operating temperature system.
FEATURES
• Fast access time (the following are maximum values)
TC55V16256JI/FTI-12:12 ns
TC55V16256JI/FTI-15:15 ns
• Low-power dissipation
(the following are maximum values)
Cycle Time 12 15 20 25 ns
Operation (max) 230 200 170 150 mA
Standby:10 mA (both devices)
• Single power supply voltage of 3.3 V ± 0.3 V
• Fully static operation
• All inputs and outputs are LVTTL compatible
• Output buffer control using OE
• Data byte control using LB (I/O1 to I/O8) and
UB (I/O9 to I/O16)
• Package:
SOJ44-P-400-1.27 (JI)
(Weight: 1.64 g typ)
TSOP II44-P-400-0.80 (FTI) (Weight: 0.45 g typ)
PIN ASSIGNMENT (TOP VIEW)
44 PIN SOJ
44 PIN TSOP
A4 1
A3 2
A2 3
A1 4
A0 5
CE ⁶
I/O1 7
I/O2 8
I/O3 9
I/O4 10
VDD 11
GND 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE ¹⁷
A15 18
A14 19
A13 20
A12 21
A16 22
44 A5
A4
43 A6
A3
42 A7
A2
41 OE
A1
40 UB
A0
39 _LB
CE
38 I/O16 I/O1
37 I/O15 I/O2
36 I/O14 I/O3
35 I/O13 I/O4
34 GND VDD
33 VDD GND
32 I/O12 I/O5
31 I/O11 I/O6
30 I/O10 I/O7
29 I/O9 I/O8
28 NU
WE
27 A8
A15
26 A9
A14
25 A10 A13
24 A11 A12
23 A17 A16
(TC55V16256JI)
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
(TC55V16256FTI)
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
VDD
I/O12
I/O11
I/O10
I/O9
NU
A8
A9
A10
A11
A17
PIN NAMES
A0 to A17 Address Inputs
I/O1 to I/O16 Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB , UB Data Byte Control Inputs
V_DD
GND
Power (+3.3 V)
Ground
NU
Not Usable (Input)
2002-01-07 1/11