TC55V16256JI Datasheet, PDF (4/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

OPERATING MODE
TC55V16256JI/FTI-12,-15
MODE
CE OE WE LB UB
I/O1 to I/O8
I/O9 to I/O16
L
L Output
Output
Read
L
L
H
H
L High Impedance
Output
L
H Output
High Impedance
L
L Input
Input
Write
L
*
L
H
L High Impedance
Input
L
H Input
High Impedance
Outputs Disable
L
H
H
*
*
High Impedance
High Impedance
L
*
*
H
H
Standby
H
*
*
*
* High Impedance
High Impedance
* : Don’t care
Note: The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8 V to the NU.
POWER
I_DDO
I_DDO
I_DDO
I_DDO
I_DDO
I_DDO
I_DDO
I_DDS
2002-01-07 4/11