TC58NVG2S3ETA00 Datasheet, PDF (59/70 Pages) Toshiba Semiconductor – 4 GBIT (512M x 8 BIT) CMOS NAND E2PROM

APPLICATION NOTES AND COMMENTS
TC58NVG2S3ETA00
(1) Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
0V
CE , WE , RE
CLE, ALE
2.7 V
2.5V
V_CC
Don’t
care
WP
Ready/Busy
V_IL
100 µs max
1 ms max
Invalid
V_IH
Operation
Don’t
care
V_IL
Don’t
care
(2) Power-on Reset
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3) Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h(71h) and FFh.
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2012-09-01